Normally you see Rds *increasing* more rapidly as you approach Vgs_off. The drain resistance is,

rds = rds0 / (1 - |Vgs|/|Vp|) ; where rds0 = 1/Yfs0 and is typically around 200 ohms

The resistor (20k to 30k) in parallel with the JFET limits the rise.

Thanks for the insight.

Knowing that I cannot exceed 417 ohm downwards, I did some calculations:

if rds0 (i suppose it's rds on) is 200 (minimum on the 2n5457), within -1.2 and -1.29 vgs (-1.3 Vpinch) I get between 2.5 k and 26 kohm. This now makes sense. Also, for me to get the jFET resistance to 417 ohm (for the notches to not exceed 20kHz), I get -0.676 vgs.

If rds0 is 333 middle case, for me to get the jFET resistance to 417 ohm, vgs is -0.26 V.

Last case is rds on 1khz (max) and I don't even have to worry about the notches, because they won't reach near 20kHz.

So if I get rdson below 417 ohm is when I need to worry, and think about diminishing the voltage span or putting a series resistance with the drain.

For a typical vintage phaser the JFET rds is probably around 10k ohm to 12k ohms. So if you reverse that calculations that means |Vgs|/|Vp| is 0.98. 2% error of adjustment in Vbias will give |Vgs|/|Vp|=0.96 and that is going to drop rds to 5k ohms. So 2% adjustment error is causing 100% change. It's extremely sensitive.

It's unlikely you will be able to eye-ball the oscilloscope voltage and transfer them to spice. Also the real JFETs have different Vgs_off and that's not be taken into account in spice.

That's why I suggest adjusting the real unit by ear. However for spice you are best working out the Vgs required to get rds=10k then setting the minimum voltage of the LFO to that number.

You say maximum rds? Or do you say rds that is equivalent to the parallel? I didn't get it. However, I understand the idea behind what you're saying. Subtle changes may be = big changes.

I'm thinkin about setting up my circuit in a way that the only preocupation I would have would be the lowest rds possible (which I already calculated as 417 ohm). If the frequency response gives me more than 20k of notch, then I will have a problem and I will want to solve it.

As I'm putting on the sims on this post, I am yes calculating the values of the LFO to give me exactly what I want (and I was able to get 1.1 Volt Span on LFO), but it isn't worth it when I know in real life there will be drastical differences (vgs off not equal tween jfets; yfs not equal tween jfets; no practical way to change resistors in a fast time; having to simulate the phasing part with a voltage source instead of the LFO, etc).

You need to think of the Vbias source as a Thevenin equivalent circuit. The bias trimpot provides a variable voltage source but the trimpot resistance means the Vbias source has a output impedance (perhaps around 50k ohm). When you probe the trimpot wipe you are probing at the output side of that 50k source impedance. In practice the 50k adds to the 1M resistor in series with the trimpot wiper so it actually ends up having little effect. If you want to check things from theoretical point of view you can replace thr trimpot with a fixed voltage source in series with say 50k but now can probe both sides of the 50k resistor.

Ok this is great, I just wanted to be able to explain this theoretically. I don't understand the meaning/importance of the impedance here. Well actually maybe I do. The "50k" adds to the 1megaohm, in that way what I dd in my sims above is correct, probed the trimpot with 50k and then to the right of 1mega, which is node Vbias.

However how does this all apply to it's function of the LFO? How could I calculate this? The LFO input is a divider from the LFO out and the Vbias +50k+1mega right? If so, the vbias has a weight of 50k+1mega and the lfo out has a weight of 3.9 mega? And how does the Vbias oscillate?

Tomorrow as soon as I can I will simulate the trimpot as a source with 50k and put results here.

Sorry for all questions but the LFO is tripping me out already.